Simulation and prototype design

FPGA based prototype

Based on FPGA simulation and prototype design, SOC system modeling and verification can be realized quickly and accurately, and the development of software and firmware can be accelerated. With the 20nm solution, virtex ultrascale vu440 FPGA and its 28nm virtex ® - 7 2000t FPGA, Xilinx takes the prototype design to the next stage. Millions of logical unit solutions:

Avoid the problem of multi chip partition in many cases

Reduces development risk for large ASIC and ASSP designs

Reduced board level space requirements and complexity

Realize flexible I / O and create adjacent devices

Reduced system level power consumption

Virtex ultrascale 440: the world's largest FPGA

Virtex ultrascale 440 devices are based on second generation stacked silicon interconnect (SSI) technology:


5.5m system logic unit, 20b transistor

48 16.3gb/s serial transceivers

89 Mb block RAM

1456 I / OS

See design examples.

Virtex-7 2000t: building with ASIC prototype
Virtex-7 2000t FPGA is realized by stack silicon interconnection (SSI), which is suitable for ASIC prototype design and simulation:

2m logic unit, 6.8b transistor

36 12.5gb/s serial transceivers

46 Mb block RAM

1200 I / OS


ASIC Simulation Implementation

With the Xilinx ultrascale? Architecture, ASIC prototype & simulation enables breakthrough performance and integration Virtex ultrascale devices simplify design partitioning with high logical capacity, over 90% device utilization, ASIC like clocks, enhanced cabling, and pin multiplexed high-speed transceivers. The breakthrough architecture integrates Xilinx vivado ® design suite to provide an ideal solution to meet the requirements of leading ASIC and SOC platforms.


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